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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Presettable Counters
MC54/74HC160 MC54/74HC162
High-Performance Silicon-Gate CMOS
The MC54/74HC160 and HC162 are identical in pinout to the LS160 and LS162, respectively. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC160 and HC162 are programmable BCD counters with asynchronous and synchronous Reset inputs, respectively. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 234 FETs or 58.5 Equivalent Gates
16 1
J SUFFIX CERAMIC PACKAGE CASE 620-10
16 1
N SUFFIX PLASTIC PACKAGE CASE 648-08
16 1
D SUFFIX SOIC PACKAGE CASE 751B-05
LOGIC DIAGRAM
ORDERING INFORMATION P0 PRESENT DATA INPUTS P1 P2 P3 3 4 5 6 14 13 12 11 Q0 Q1 Q2 Q3 RIPPLE CARRY OUT BCD OR BINARY OUTPUTS MC54HCXXXJ MC74HCXXXN MC74HCXXXD Ceramic Plastic SOIC
PIN ASSIGNMENT
RESET CLOCK P0 P1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RIPPLE CARRY OUT Q0 Q1 Q2 Q3 ENABLE T LOAD
CLOCK
2
15
RESET LOAD COUNT ENABLES ENABLE P ENABLE T PIN 16 = VCC PIN 8 = GND
P2 P3 ENABLE P GND
10/95
(c) Motorola, Inc. 1995
IIIIIIIIIII II IIIII I I IIIIIIIIIII II IIIIIIIIIII II IIIIIIIIIII II IIIIIIIIIII II IIIIIIIIIII II IIIIIIIIIII II IIIIIIIIIII II IIIIIIIIIII IIIIIII I IIIIIIIIIII II IIIIIIIIIII II IIIIIIIIIII II
Device HC160 HC162 Count Mode BCD BCD Reset Mode Asynchronous Synchronous
FUNCTION TABLE
Inputs Clock Reset* L H H H H Load X L H H H Enable P X X H L X Enable T X X H X L Output Q Reset Load Preset Data Count No Count No Count
* HC162 only. HC160 is an Asynchronous Reset Device H = high level L = low level X = don't care
1
REV 6
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Vin = VCC or GND 6.0 8 80 160 A Iout = 0 A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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MAXIMUM RATINGS*
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MC54/74HC160 MC54/74HC162
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
VOL
ICC
TA
VIH
VIL
Iin
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP)
Storage Temperature
Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 1)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND
Vin = VIH or VIL |Iout| |Iout|
Vin = VIH or VIL |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
v
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 1.5 to VCC + 1.5
- 65 to + 150
- 0.5 to + 7.0
2 - 55 Min 2.0 Value
v 4.0 mA v 5.2 mA
v 4.0 mA v 5.2 mA
0 0 0
0
50
25
20
260 300
750 500
+ 125
1000 500 400
VCC
Max
6.0
VCC V
6.0
4.5 6.0
2.0 4.5 6.0
4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.1
1.5 3.15 4.2
0.26 0.26
3.98 5.48
0.1 0.1 0.1
1.9 4.4 5.9
0.3 0.9 1.2
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
v
1.0 1.5 3.15 4.2 0.40 0.40 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
v
Unit
A V V V V
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol tTLH, tTHL tPHL tPHL tPLH tPHL tPLH tPHL tPHL tPLH fmax Cin Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 7) Maximum Propagation Delay, Reset to Ripple Carry Out (HC160 Only) (Figures 2 and 7) Maximum Propagation Delay, Clock to Ripple Carry Out (Figures 1 and 7) Maximum Propagation Delay, Enable T to Ripple Carry Out (Figures 3 and 7) Maximum Propagation Delay, Reset to Q (HC160 Only) (Figures 2 and 7) Maximum Propagation Delay, Clock to Q (Figures 1 and 7) Maximum Clock Frequency (50% Duty Cycle)* (Figures 1 and 7) Parameter VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 --
High-Speed CMOS Logic Data DL129 -- Rev 6 CPD Power Dissipation Capacitance (Per Package)*
* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
* Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine f max. However, if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the f max in the table above is applicable. See Applications Information in this data sheet. NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
3 - 55 to 25_C Typical @ 25C, VCC = 5.0 V 220 44 37 215 43 37 175 35 30 195 39 33 160 32 27 210 42 36 205 41 35 170 34 29 6.0 30 35 10 75 15 13 Guaranteed Limit 275 55 47 270 54 46 220 44 37 245 49 42 200 40 34 265 53 45 255 51 43 215 43 37 4.8 24 28 10 95 19 16 60 330 66 56 325 65 55 265 53 45 295 59 50 240 48 41 315 63 54 310 62 53 255 51 43 110 22 19 4.0 20 24 10
MC54/74HC160 MC54/74HC162
v 85_C v 125_C
MOTOROLA MHz Unit pF pF ns ns ns ns ns ns
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
MOTOROLA
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
MC54/74HC160 MC54/74HC162
Symbol
trec
trec
tr, tf
tsu
tsu
tsu
tsu
tw
tw
th
th
th
th
Maximum Input Rise and Fall Times (Figure 1)
Minimum Pulse Width, Reset (HC160 only) (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Minimum Recovery Time, Load Inactive to Clock (Figure 5)
Minimum Recovery Time, Reset Inactive to Clock (HC160 only) (Figure 2)
Minimum Hold Time, Clock to Enable T or Enable P (Figure 6)
Minimum Hold Time, Clock to Reset (HC162 only) (Figure 4)
Minimum Hold Time, Clock to Load (Figure 5)
Minimum Hold Time, Clock to Preset Data Inputs (Figure 5)
Minimum Setup Time, Enable T or Enable P to Clock (Figure 6)
Minimum Setup Time, Reset to Clock (HC162 only) (Figure 4)
Minimum Setup Time, Load to Clock (Figure 5)
Minimum Setup Time, Preset Data Inputs to Clock (Figure 5)
Parameter
4 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C 1000 500 400 125 25 21 125 25 21 200 40 34 160 32 27 135 27 23 150 30 26 80 16 14 80 16 14 50 10 9 3 3 3 3 3 3 3 3 3
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1000 500 400 100 20 17 100 20 17 155 31 26 155 31 26 250 50 43 200 40 34 170 34 29 190 38 33 65 13 11 3 3 3 3 3 3 3 3 3 1000 500 400 120 24 20 120 24 20 190 38 32 190 38 32 300 60 51 240 48 41 205 41 35 225 45 38 75 15 13 3 3 3 3 3 3 3 3 3 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
MC54/74HC160 MC54/74HC162
FUNCTION DESCRIPTION
The HC160/162 are programmable 4-bit synchronous counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading, and count- enable controls. The HC160 and HC162 are BCD counters with asynchronous Reset, and synchronous Reset, respectively. INPUTS Clock (Pin 2) The internal flip-flops toggle and the output count advances with the rising edge of the Clock input. In addition, control functions, such as resetting (HC162) and loading occur with the rising edge of the Clock input. Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6) These are the data inputs for programmable counting. Data on these pins may be synchronously loaded into the internal flip-flops and appear at the counter outputs. P0 (pin 3) is the least-significant bit and P3 (pin 6) is the most-significant bit. OUTPUTS Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11) These are the counter outputs (BCD or binary). Q0 (pin 14) is the least-significant bit and Q3 (pin 11) is the most-significant bit. Ripple Carry Out (Pin 15) When the counter is in its maximum state (1001 for the BCD counters or 1111 for the binary counters), this output goes high, providing an external look-ahead carry pulse that may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count state. The logic equation for this output is: Ripple Carry Out = Enable T Q0 Q1 Q2 Q3 for BCD counters HC160 and HC162
Load H L X X
CONTROL FUNCTIONS Resetting A low level on the Reset pin (pin 1) resets the internal flip- flops and sets the outputs (Q0 through Q3) to a low level. The HC160 resets asynchronously and the HC162 resets with the rising edge of the Clock input (synchronous reset). Loading With the rising edge of the Clock, a low level on Load (pin 9) loads the data from the Preset Data Input pins (P0, P1, P2, P3) into the internal flip-flops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low. Although the HC160 and HC162 are BCD counters, they may be programmed to any state. If they are loaded with a state disallowed in BCD code, they will return to their normal count sequence within two clock pulses (see the Output State Diagram). Count Enable/Disable These devices have two count-enable control pins: Enable P (pin 7) and Enable T (pin 10). The devices count when these two pins and the Load pin are high. The logic equation is: Count Enable = Enable P Enable T Load The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count- enable control; Enable T is both a count-enable and a Ripple-Carry Output control. Table 1. Count Enable/Disable
Control Inputs Enable P H H L X Enable T H H H L Result at Outputs Q0 - Q3 Count No Count No Count No Count Ripple Carry Out High when Q0 - Q3 are maximum* High when Q0 - Q3 are maximum* L
* Q0 through Q3 are maximum for the HC160 and HC162 when Q3 Q2 Q1 Q0 = 1001.
OUTPUT STATE DIAGRAMS HC160 and HC162 BCD Counters
0 1 2 3 4
15
5
14
6
13
7
12
11
10
9
8
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC54/74HC160 MC54/74HC162
SWITCHING WAVEFORMS
tr 90% 50% 10% tw 1/fmax tPLH tPHL ANY OUTPUT 90% 50% 10% tTLH tTHL ANY OUTPUT tf VCC GND RESET tPHL 50% trec VCC CLOCK 50% GND 50% GND tw VCC
CLOCK
Figure 1.
tr ENABLE T 90% 50% 10% tPLH 90% 50% 10% tTLH tf VCC GND tPHL CLOCK tTHL tsu RESET 50%
Figure 2.
th VCC 50% GND
RIPPLE CARRY OUT
Figure 3.
Figure 4. HC162 Only
VALID INPUTS P0, P1, P2, P3 VCC 50% GND tsu LOAD 50% GND tsu CLOCK th 50% GND trec VCC th VCC ENABLE T OR ENABLE P 50% GND tsu CLOCK th VCC 50% GND VALID VCC
Figure 5. TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST CL*
Figure 6.
* Includes all probe and jig capacitance
Figure 7.
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54HC160 * MC74HC160 BCD Counter with Asynchronous Reset
Q0 14 Q0
High-Speed CMOS Logic Data DL129 -- Rev 6 Q0 T0 R C C LOAD LOAD P0 Q1 13 Q1 T1 R C C LOAD LOAD P1 Q1 Q2 12 Q2 T2 R C C LOAD LOAD P2 Q2 Q3 11 Q3 Q3 15 RIPPLE CARRY OUT T3 R C C LOAD LOAD P3 VCC = PIN 16 GND = PIN 8 R C C LOAD LOAD The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle- Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low.
P0
3
P1 4
P2
5
7
P3
6
ENABLE P
7
ENABLE T
10
RESET
1
CLOCK
2
MC54/74HC160 MC54/74HC162
MOTOROLA
LOAD
3
MC54/74HC160 MC54/74HC162
HC160, HC162 TIMING DIAGRAM
Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to BCD seven. 3. Count to eight, nine, zero, one, two, and three. 4. Inhibit. RESET (HC160) RESET (HC162) LOAD
(ASYNCHRONOUS) (SYNCHRONOUS)
P0 PRESET DATA INPUTS P1 P2 P3 CLOCK (HC160) CLOCK (HC162)
COUNT ENABLES
ENABLE P ENABLE T Q0 Q1
OUTPUTS Q2 Q3 RIPPLE CARRY OUT RESET
7 LOAD
8
9
0
1
2
3 INHIBIT
COUNT
MOTOROLA
8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54HC160 * MC74HC160 BCD Counter with Synchronous Reset
14
Q0
Q0
High-Speed CMOS Logic Data DL129 -- Rev 6 Q0 T0 R C C LOAD LOAD P0 Q1 13 Q1 Q1 T1 R C C LOAD LOAD P1 Q2 12 Q2 Q2 T2 R C C LOAD LOAD P2 Q3 11 Q3 Q3 15 RIPPLE CARRY OUT T3 R C C LOAD LOAD P3 VCC = PIN 16 GND = PIN 8 R C C LOAD LOAD The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle- Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low.
P0
3
P1
4
5
9
P2
P3
6
ENABLE P
7
ENABLE T
10
RESET
1
CLOCK
2
MC54/74HC160 MC54/74HC162
MOTOROLA
LOAD
3
MC54/74HC160 MC54/74HC162
TYPICAL APPLICATIONS CASCADING N-Bit Synchronous Counters
LOAD INPUTS INPUTS INPUTS
LOAD H = COUNT L = DISABLE H = COUNT L = DISABLE
P0 P1 P2 P3
LOAD
P0 P1 P2 P3
LOAD
P0 P1 P2 P3
ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT
ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT
ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT TO MORE SIGNIFICANT STAGES
RESET OUTPUTS CLOCK NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and Clock. OUTPUTS OUTPUTS
Nibble Ripple Counter
INPUTS LOAD ENABLE P ENABLE T LOAD P0 P1 P2 P3 LOAD
INPUTS
INPUTS
P0 P1 P2 P3
LOAD
P0 P1 P2 P3
ENABLE P ENABLE T CLOCK CLOCK R RESET Q0 Q1 Q2 Q3 RIPPLE CARRY OUT
ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT
ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT TO MORE SIGNIFICANT STAGES
OUTPUTS
OUTPUTS
OUTPUTS
MOTOROLA
10
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC160 MC54/74HC162
TYPICAL APPLICATION
HC162
OTHER INPUTS Q0 Q1 Q2 Q3 RESET OPTIONAL BUFFER FOR NOISE REJECTION OUTPUT
Modulo-5 Counter
The HC162 facilitates designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous Reset.
High-Speed CMOS Logic Data DL129 -- Rev 6
11
MOTOROLA
MC54/74HC160 MC54/74HC162
OUTLINE DIMENSIONS
-A -
16 9
J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V
-B - C L
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51
-T
SEATING - PLANE
N E F G D 16 PL 0.25 (0.010)
M
K M J 16 PL 0.25 (0.010)
M
TB
S
TA
S
DIM A B C D E F G J K L M N
-A -
16 9
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
MOTOROLA
12
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC160 MC54/74HC162
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
13
*MC54/74HC160/D*
MC54/74HC160/D MOTOROLA

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